April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA
DesignCon 2022 Schedule Builder
Welcome to the DesignCon 2022 agenda and presentation download site. Here you can view and download conference, Chiphead Theater, and other event presentations before, during, and after the event. If you're looking for a presentation from a specific session that you're unable to find here, it is likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalog of available presentations.
Masashi Shimanouchi, Design Engineer, Intel
Masashi Shimanouchi is a design engineer at Intel Corporation. His work on high-speed serial links of FPGA products includes link system and component architecture, modeling, characterization, and link jitter and BER simulation tools development with expertise in measurement metrology, signal processing, signal integrity and jitter area.
Presenting:
- 224Gbps-PAM4 End-to-end Channel Solutions for High-density Networking System
- Current Limitation & New Method to Accurately Estimate Reference Signal Jitter for 100+ Gbps 802.3 & OIF/CEI Interference Tolerance Test
- Generalized ccICN (Component Contribution Integrated Crosstalk Noise)
- Next Generation 224Gbps-PAM4 SERDES, Channel & Link Systems
