DesignCon is part of the Informa Markets Division of Informa PLC

This site is operated by a business or businesses owned by Informa PLC and all copyright resides with them. Informa PLC's registered office is 5 Howick Place, London SW1P 1WG. Registered in England and Wales. Number 8860726.

Welcome to the DesignCon 2020 agenda and presentation download site. Here you can view and download conference and/or Chiphead Theater presentations before, during, and after the event. If you’re looking for a presentation from a specific session that you’re unable to find here, it is likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalogue of available presentations.

Anna WongSenior Engineer ManagerXilinx Inc

Anna Wong is a senior engineer manager at Xilinx Inc. responsible for on-die noise, jitter and HBM channel timing and characterization. Prior to that, she worked in analog design at Xilinx Inc. and managed a team that designed PLL IP blocks. She received her MSEE degree from Stanford University.