April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA
DesignCon 2022 Schedule Builder
Welcome to the DesignCon 2022 agenda and presentation download site. Here you can view and download conference, Chiphead Theater, and other event presentations before, during, and after the event. If you're looking for a presentation from a specific session that you're unable to find here, it is likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalog of available presentations.
Hsinho Wu, Design Engineer, Intel
Dr. Hsinho Wu is a design engineer at Intel Corporation. He presently works on high-speed communication systems of FPGA products. His development and research interests include signal integrity, clock and data recovery, equalizations, system modeling and simulation techniques. Dr. Wu was with National Semiconductor from 1999-2011 where he developed high speed interface products.
Presenting:
- 224Gbps-PAM4 End-to-end Channel Solutions for High-density Networking System
- COM-based IBIS-AMI for 106/112Gbps System Compliance
- Current Limitation & New Method to Accurately Estimate Reference Signal Jitter for 100+ Gbps 802.3 & OIF/CEI Interference Tolerance Test
- Next Generation 224Gbps-PAM4 SERDES, Channel & Link Systems
- Receiver Calibration & Testing Methodologies Comparison for PAM-4 IOs
- Transmitter Jitter Measurement Methodologies for PAM-4 IOs
