DesignCon 2022 Schedule Builder

Shin Wu is a Staff Digital Engineer at Northrop Grumman Digital Technology Department. He is a senior member of the ASIC Physical Design team and is currently the Technical Lead for large multi-year ASIC development program at Northrop Grumman. Shin has broad experience in ASIC design from RTL to GDSII design, implementation and sign-off verification including tape-out processing to ASIC foundries. He is a specialist in Static Timing Analysis, IR/EM Analysis, Place & Route, Low Power Design and Physical Verification. Shin is a key contributor to defining, implementing and deploying a common ASIC design implementation flow currently used by multiple ASIC development efforts at Northrop Grumman. Shin has BSEE from University of Maryland and MS in Computer Engineering from Johns Hopkins University.

Presenting:

• Improved Methodology to Accurately Perform System Level Power Integrity Analysis Including an ASIC Die