April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA
DesignCon 2022 Schedule Builder
Welcome to the DesignCon 2022 agenda and presentation download site. Here you can view and download conference, Chiphead Theater, and other event presentations before, during, and after the event. If you're looking for a presentation from a specific session that you're unable to find here, it is likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalog of available presentations.
Zuoguo (Joe) Wu, Senior Principal Engineer, Intel
Dr. Zuoguo (Joe) Wu is a Senior Principal Engineer and Manager of an I/O Circuits and Protocol team at Intel Data Platform Group. His responsibilities are in the physical layer link architecture and I/O standards and specifications of client and server CPUs and chipsets, including high speed serial interfaces, in-package memory I/O, and low power multi-chip package interfaces. Prior to Intel, he designed computer disk drive, wireless, and optical communication ICs. He has over 30 patents issued.
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