Welcome to the DesignCon 2020 agenda and presentation download site. Here you can view and download conference and/or Chiphead Theater presentations before, during, and after the event. If you’re looking for a presentation from a specific session that you’re unable to find here, it is likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalogue of available presentations.
Eli Zalianski is an Electrical Validation engineer developing test methodology. He is responsible for HSIO PHY interconnect testing, silicon bring-up, and characterization. Eli specialized in 100Gbps/25Gbps PAM4/NRZ Ethernet protocols, PCIe Gen4, and DDR4/LPDDR4 JEDEC compliance testing. Eli’s experience with the channel operating margin (COM) methodology and machine learning algorithms was used to produce the data for this paper.He joined Intel in 2015 and received his BSc in Electrical Engineering from the Technion – Israel Institute of Technology in 2017.