DesignCon 2022 Schedule Builder

Dr. Iliya Zamek held various engineering and management roles in the design of measurement instrumentation and ATE in his early career, worked on Jitter and Signal Integrity, and pioneered new approaches to Jitter characterization and mitigation. He held multiple roles in Q-Tech, Altera, Semtech, Inphi, Intel, doing Product Engineering & NPI, including design, validation, and development of XO, PLL and CDR, FPGA, ASIC, 40G, 100G, and 400G SERDES, optical and electrical 100/400G Transceivers. He’s done extensive research on Power-induced Jitter and Power Integrity methodology. Since 2006 he has been a co-chair & co-organizer of DesignCon tracks on Measurement Methodology and Power Integrity. Dr. Zamek published more than 50 papers and has been awarded 20 patents.

Presenting:

• New Power Integrity Methodology & Mitigation Effect of PDN Voltage Decay